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document id#: 080152 date: sep 19, 2007 rev: o version: 2 distribution: public document ? le79r79 ringing subscriber line interface circuit ve580 series applications ? ideal for short-loop applications ? ideal for isdn-ta and fixed radio access applications ? integrated access devices (iads) ? network interface units (nius) ? cable modems ? dsl modems ? set top / house side boxes ? intelligent pbx ? pain gain ? fxs cards ? voice over isdn or t1/e1 ? smart residential gateways ? wll, apon, fitl, ngn, and all other short-loop cpe/ enterprise telephony applications features ? through trapezoidal ringing ? on-chip ring-trip detector ? low standby state power ? battery operation: ?v bat1 : ?40.5 to ?75 v ?v bat2 : ?19 v to v bat1 ? on-chip battery switching and feed selection ? on-hook transmission ? two-wire impedance set by single external impedance ? programmable constant-current feed ? programmable open circuit voltage ? programmable loop-detect threshold ? current gain = 1000 ? ground-key detector ? polarity reversal option available ? internal v ee regulator (no external ?5 v power supply required) related literature ? 080917 ve790 series rslic device product brief ? 080158 le79r70/79/100/ 101 technical overview ? 080914 le79r79 rslic device user?s guide ? 080810 le71hr0021 reference design user?s guide ? 080255 le71he0040j evaluation board user?s guide ? 080458 le79r100/101 v. le79r79 comparison brief ? 080753 le58ql02/021/031 qlslac? data sheet ordering information -1: 52 db longitudinal balance, polarity reversal -2: 63 db longitudinal balance, polarity reversal -3: 52 db longitudinal balance, no polarity reversal 1. zarlink reserves the right to fulfill all orders for this device with parts marked with the "am" part number prefix until all inventory bearing this mark has been depleted. note that parts marked with either the "am" or the "le" part number prefix are equivalent devices in terms of form, fit, and function?the prefix appearing on the topside mark is the only difference. 2. due to size constraints, qfn dev ices are marked by omitting the ?le? prefix and the performance grade dash character. for example, le79r79-1fqc is marked 79r791fqc. 3. the green package meets rohs directive 2002/95/ec of the european council to minimize the environmental impact of electrical equipment. 4. for delivery using a tape and reel packing system, add a "t" suffix to the opn (ordering part number) when placing an order. device 1 package type 2, 3 packing 4 le79r79-1djc 32-pin plcc (green package) tube LE79R79-2DJC le79r79-3djc le79r79-1fqc 32-pin qfn (green package) tray le79r79-2fqc description the le79r79 ringing slic device is a bipolar monolithic slic that offers on-chip ringing. designers can achieve significant cost reductions at the system level for short- loop applications by integrating the ringing function on chip. examples of such applications would be isdn terminal adaptors, fiber-in-the- loop, radio-in-the-loop, hybrid fiber/coax and video telephony (home-side) boxes. the le79r79 ringing slic device can provide sufficient voltage to meet the stringent lssgr five- ringer equivalent specification. using a cmos-compatible input waveform and wave shaping r-c network, the le79r79 ringing slic device can provide trapezoidal wave ringing to meet various design requirements. see the le79r79 block diagram , on page 4 .
le79r79 data sheet 2 zarlink semiconductor inc. table of contents applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 transmission performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 longitudinal performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 idle channel noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 insertion loss and four-to-four-wire balance return signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 line characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 power supply rejection ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 logic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 ring-trip detector input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 ring signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 ground-key detector thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 loop detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 relay driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 relay driver schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 slic device decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 user-programmable components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 dc feed characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 ring-trip components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 le79r79 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 application circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 physical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 32-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 32-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision b to c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision c to d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision d to e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision e to f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision f to g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision g to h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision h to i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision i to j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision j1 to k1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision k1 to l1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision l1 to m1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision m1 to n1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
le79r79 data sheet 3 zarlink semiconductor inc. revision n1 to n2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 revision n2 to o1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 revision o1 to o2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
le79r79 data sheet 4 zarlink semiconductor inc. product description the zarlink family of subscriber line interface circuit (slic) products provide the telephone interface functions required throughout the worldwide market. zarlink slic devices address all major telephony markets including central office (co), private branch exchange (pbx), digital loop carrier (dlc), fiber-in-the- loop (fitl), radio-in-the-loop (r itl), hybrid fiber coax (hfc), and video telephony applications. the zarlink slic devices offer support of borsht (battery feed, overvoltage protection, ringing, supervision, hybrid, and test) functions with features includin g current limiting, on-hook transmission, polari ty reversal, tip open, and loop-current detecti on. these features allow reduction of linecard cost by minimi zing component count, conservi ng board space, and supporting automated manufacturing. the zarlink slic devices provide the two- to four-wire hybrid function, dc-loop feed, and two-wire supervision. two-wire termination is programmed by a scaled impedance network. transhyb rid balance can be achieved with an external balance circuit or simply programmed using a companion zarlink codec/filter, such as the le58ql0xx quad slac (qlslac?) device. the le79r79 ringing slic device is a bipolar monolithic slic that offers on-chip ringing. now designers can achieve significant cost reductions at the system level for shor t-loop applications by inte grating the ringing function on chip. examples of such applications would be isdn terminal adaptors, fiber-in-the-loop, radio-in-the-loop, hybr id fiber/coax and video telephony (home - side) boxes. the le79r79 ringing slic can provide sufficient voltage to meet the stringent lssgr five-ringer equivalent specification. using a cmos-c ompatible input waveform and wave shaping r-c network, the le79r79 ringing slic can provide trapezoidal wave ringing to meet various design requirements. in order to further enhance the suitabil ity of this device in short-loop, distrib ute d switching applications, zarlink has maximized power savings by incorporating battery switching on chip . the le79r79 ringing slic device switches between two battery supplies such that in the off-hook (active) state, a low battery is used to save power. in order to meet the open circuit volta ge requirements of fax machines and maintenance termination units (mtu), the slic device auto matically switches to a higher voltage in the on-hook (standby) state. like all of the zarlink slic devices, the le79r79 r inging slic d evice supports on-ho ok transmission, ring-tri p d etection, programmable loop-detect threshold, and is available with on-chip polarity reversal. the le79r79 ringing slic device is a programmable constant-current feed device with two on-chip rela y drivers to operate external relays. several performance grades are available to meet both ccitt and lssgr requirements, including various longitudinal balance options. figure 1. le79r79 block diagram two-wire interface ring-trip detector ground-key detector off-hook detector signal transmission power-feed controller switch driver rtrip1 rtrip2 a(tip) hpa hpb b(ring) vbat2 vbat1 vcc vneg bgnd agnd/dgnd relay driver relay driver input decoder and control ryout2 rye ryout1 d1 d2 c1 c2 c3 e1 rd vtx rsn ringin rdc rdcr rsgl rsgh det b2en
le79r79 data sheet 5 zarlink semiconductor inc. connection diagrams note: 1. pin 1 is marked for orientation. 2. nc = no connect. 3. the thermally enhanced qfn package feat ures an exposed pad on the underside which must be electrically tied to vbat1. ryout2 vcc vbat2 bgnd b(ring) a(tip) rd 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 c1 d2 nc rsgh rsgl rdc agnd/dgnd rtrip1 rtrip2 hpb hpa ringin rdcr vtx vneg rsn det vbat1 rye ryout1 32-pin plcc b2en d1 e1 c3 c2 exposed pad 32-pin qfn 1 21 20 19 18 17 22 23 24 2 3 4 5 6 7 8 10 912 11 14 13 16 15 32 31 30 29 28 27 26 25 top view rsn vneg vtx rdcr ringin hpa hpb rtrip2 e1 c3 c2 rye ryout1 b2en vbat1 d1 rtrip1 ax rd bx vbat2 bgnd vcc ryout2 det c1 d2 agnd rsgl rdc nc rsgh
le79r79 data sheet 6 zarlink semiconductor inc. pin descriptions pin names type description agnd/dgnd ground analog and digital ground a(tip) output output of a(tip) power amplifier b2en input v bat2 enable. logic low enables operation from v bat2 . logic high enables operation from v bat1 . ttl compatible. bgnd ground battery (power) ground b(ring) output output of b(ring) power amplifier c3?c1 input decoder. slic control pins. c3 is msb and c1 is lsb. ttl compatible. d1 input relay1 control. ttl compatible. logic low activates the relay1 relay driver. d2 input relay2 control. (option) ttl compatible . logic low activates the relay2 relay driver. det output hook switch detector. when enabled, a logic low indica tes that the selected detector is tripped. the logic inputs c3?c1 and e1 select the detector. the output is open collector with a built-in 15 k ?
le79r79 data sheet 7 zarlink semiconductor inc. electrical characteristics absolute maximum ratings stresses greater than those listed under absolute maximum ra tings can cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi mum ratings for extended periods can affect device reliability. note: 1. thermal limiting circuitry on the chip wi ll shut down the circuit at a junction temperature of about 165oc. continuous operat ion above 145oc junction temperature may degrade device reliability. 2. the thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. specified performance requires that the exposed thermal pad be soldered to an equally sized exposed copper surface, whic h, in turn, conducts heat thr ough multiple vias to a large internal copper plane. package assembly green package devices are assembled with enhanced, environmen tal compatible lead-free, halogen-free, and antimony-free materials. the leads possess a matte-tin plating which is comp atible with conventional board a ssembly processes or newer lead- free board assembly processes. the peak soldering temperature should not exceed 245c during printed circuit board assembly. refer to ipc/jedec j-std-020b table 5-2 for the recommended solder reflow temperature profile. storage temperature ?55 to + + + + + + + + + + + +
le79r79 data sheet 8 zarlink semiconductor inc. operating ranges zarlink guarantees the performance of this device over commercial (0 to 70o c) and ind ustrial (-40 to 8 5oc) temperature ranges by conducting electrical characterization over each range and by conducting a produc tion test with single insertion coupled to periodic sampling. these characterization and test procedures comply with section 4.6.2 of bellcore gr-357-core component reliability assurance requirements for telecommunications equipment. environmental ranges electrical ranges specifications transmission performance ambient temperature 0 to 70c commercial ?40 to +85 c extended temperature ambient relative humidity 15 to 85% v cc 4.75 to 5.25 v v neg ?4.75 v to v bat2 v bat1 ?40.5 to ?75 v v bat2 ?19 v to v bat1 agnd/dgnd 0 v bgnd with respect to agnd/dgnd ?100 to 100 mv load resistance on vtx to ground 20 k : minimum description test conditions (see note 1) min typ max unit note 2-wire return loss 200 hz to 3.4 khz (see figure 6.) 26 db 1, 4, 6 z vtx , analog output impedance 320 : 4 v vtx , analog output offset voltage 0 to 70 c ?35 35 mv 40 to 85 c ?40 40 4 z rsn , analog input impedance 120 : overload level, 2-wire and 4-wire, off hook active state 2.5 vpk 2a overload level, 2-wire on hook, r lac = 600 : 0.88 vrms 2b thd (total harmonic distortion) 3 dbm, bat 2 = 24 v ?64 ?50 db 5 thd, on hook, oht state 0dbm, r lac = 600 : bat1 = 75 v ?40
le79r79 data sheet 9 zarlink semiconductor inc. longitudinal performance (see figure 8.) idle channel noise insertion loss and four-to-four-w ire balance return signal (see figure 6 and figure 7.) description test conditions (see note 1) min typ max unit note longitudinal to metallic l-t, l-4 balance 200 hz to 3.4 khz ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? + ?/ + + + ? + + + ? + + + + + ? + + + + + ? + + + + ? + + + +
le79r79 data sheet 10 zarlink semiconductor inc. line characteristics power supply rejection ratio (v ripple = 100 mvrms), active normal state power dissipation description test conditions (see note 1) min typ max unit note i l , loop-current accuracy i l in constant-current region, b2en=0 0.87i l i l 1.085i l ma i l , long loops, active state r ldc = 600 ? ? ? + ? ? ? ? ? ? ? ? ? r l 400 + -------------------------------------- =
le79r79 data sheet 11 zarlink semiconductor inc. supply currents logic inputs (applies to c3?c1, d2?d1, e1, and b2en). logic output ( det ) ring-trip detector input ring signal ground-key detector thresholds description test conditions (see note 1) min typ max unit note i cc , on-hook v cc supply current open circuit state 3.0 4.5 ma standby state 3.2 5.5 oht state 6.2 8.0 active state-normal 6.5 9.0 i neg , on-hook v neg supply current open circuit state 0.1 0.2 standby state 0.1 0.2 oht state 0.7 1.1 active state-normal 0.7 1.1 i bat , on-hook v bat supply current open circuit state 0.45 1.0 standby state 0.6 1.5 oht state 2.0 4.0 active state-normal 2.7 5.0 description test conditions min typ max unit note v ih , input high voltage 2.0 v v il , input low voltage 0.8 i ih , input high current ?75 40 a i il , input low current ?400 description test conditions (see note 1) min typ max unit note v ol , output low voltage i out = 0.8 ma, 15 k ? ? ? ? ? ? ? rrt1 --------------------------- - 24 + ?? ?? ? = ? ? ? gain ( )
le79r79 data sheet 12 zarlink semiconductor inc. loop detector relay driver output (relay 1 and 2) relay driver schematic note: 1. unless otherwise noted, test conditions are bat1 = ?75 v, bat2 = ?24 v, v cc = +5 v, v neg = ?5 v, r l = 600 ? ? ? ? ? ? ? ? ? ? ? ? ? + + + + + ? ? ?
le79r79 data sheet 13 zarlink semiconductor inc. 2. a. overload level is defined when thd = 1%. b. overload level is defined when thd = 1.5%. 3. balance return signal is the signal generated at v tx by v rx . this specification assumes that t he two-wire ac load impedance matches the programmed impedance. 4. not tested in production. this parameter is guarant eed by characterization or correlation to other tests. 5. this parameter is tested at 1 khz in production. perf ormance at other frequencies is guaranteed by characterization. 6. group delay can be greatly reduced by using a z t network such as that shown in note 1 above. the network reduces the group delay to less than 2 s and increases 2wrl. the effect of group delay on linecard performance may also be compensated for by synthesizin g complex impedance with the qslac or dslac device. 7. 70 vpk provides 50 vrms with a crest factor of 1.25 to a load of 1400 ? ? ? ?
le79r79 data sheet 14 zarlink semiconductor inc. user-programmable components z t is connected between the vtx and rsn pins. the fuse resistors are r f , and z 2win is the desired 2-wire ac input impedance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. z rx is connected from v rx to r sn . z t is defined above, and g 42l is the desired receive gain. r dc1 , r dc2 , and c dc form the network connected to the rdc pin. i loop is the desired loop current in the constant-current region. r dcr1 , r dcr2 , and c dcr form the network connected to the r dcr pin. see application circuit , on page 21. for these components. c dcr sets the ringing time constant, which can be between 15 s and 150 s. for high battery state r d is the resistor connected from the rd pin to gnd and r lth is the loop-resistance threshold between on-hook and off-hook detection. r d should be greater than 56 k ? ? () ? () ---------------------------------------------------- ? + 3000 i ringlim ----------------------- = c dc 19 ms r dc1 r dc2 + r dc1 r dc2 ----------------------------------- ? = c dcr r dcr1 r dcr2 + r dcr1 r dcr2 ------------------------------------------ - ? ? ? 915 ----------------------------- - r d ? ? ? =
le79r79 data sheet 15 zarlink semiconductor inc. dc feed characteristics figure 3. typical v ab vs. i l dc feed characteristics i l (ma) 0 30 50 v ab (volts) 2) v asl 3) v appl 40 30 20 10 5) v apph 4) v ash high battery anti-sat low battery anti-sat 1) constant-current region notes: 1. constant-current region: where 2. low battery where r sgl = resistor to gnd, b2en = logic low. anti-sat region: where r sgl = resistor to v cc , b2en = logic low. r sgl to v cc must be greater than 100 k ? ? r dc r dc1 r dc2 20 k ? 80 k ? 100 k ? = + = + = v bat1 75 v v bat2 24 v ? = , ? = () v ab i l r l 2500 rdc ------------ - r l ; == r l r l =2r f , + v asl 1000 104 10 3 ? r sgl + () ? 6720 10 3 ? 80 r sgl ? () + ----------------------------------------------------------------- - ; = v asl 1000 r sgl 56 10 3 ? ? () ? 6720 10 3 ? 80 r sgl ? () + -------------------------------------------------------------- - ; = v appl 4.17 v asl + = i loopl v appl r dc1 r dc2 + () 600 -------------------------------------- 2 r f r loop ++ ------------------------------------------------------------------------------- = v ash v ashh v asl + = v ashh 1000 70 10 3 ? r sgh + () ? 1934 10 3 ? 31.75 r sgh ? () + ---------------------------------------------------------------------- - ; = v ashh 1000 r sgh 2.75 10 3 ? + () ? 1934 10 3 ? 31.75 r sgh ? () + ---------------------------------------------------------------------- - ; = v apph 4.17 v ash + = i looph v apph r dc1 r dc2 + () 600 -------------------------------------- 2 r f r loop ++ ------------------------------------------------------------------------------- =
le79r79 data sheet 16 zarlink semiconductor inc. ring-trip components where r lrt = loop-detection threshold resistance for ring trip and cf = crest factor of ringing signal ( ) ? ? ? k ? ? 15 () ? ? ? () ? ------------------------------------------------------------------------------------------------------------------------------- ---------------- - ? ? () ? = 0 battery ringing reference (input to r slew ) a(tip) this is the best time for switching between ringing and other states for minimizing detect switching transients. b(ring) r l a (tip) b (ring) rdc slic i l rsn r dc1 c dc r dc2 a b feed current programmed by r dc1 and r dc2
le79r79 data sheet 17 zarlink semiconductor inc. test circuits figure 6. two-to-four-wire insertion loss figure 7. four-to-two-wire insertion loss and four-to-four-wire balance return signal figure 8. longitudinal balance slic a (tip) vtx agnd rsn v ab r t r rx i l2-4 = 20 log(v tx / v ab ) r l 2 r l 2 v l b (ring) slic a (tip) vtx agnd r sn v ab r t r rx i l4-2 = 20 log(v ab / v rx ) b (ring) brs = 20 log(v tx / v rx ) v rx r l slic a (tip) vtx agnd r sn v ab r t r rx l -t long. bal. = - 20 log(v ab / v l ) b (ring) v r x r l 2 r l 2 v l v l s1 1 - 20 log(v tx / v l ) s2 open, s1 closed s2 closed, s1open 4-l long. sig. gen. = 20 log(v l / v rx ) c
le79r79 data sheet 18 zarlink semiconductor inc. figure 9. two-wire retu rn loss test circuit figure 10. loop-detector switching figure 11. ground-key switching return loss = ?20 log (2v m / v s ) z d : the desired impedance; eg., the characteristic impedance of the line slic a (tip) vtx agnd rsn r rx b (ring) c t1 r t1 r t2 v m z in z d v s r r a (tip) b (ring) e1 r l = 600 ? ?
le79r79 data sheet 19 zarlink semiconductor inc. figure 12. rfi test circuit 1.5 vrms 80% amplitude modulated 1 00 khz to 30 mhz hf gen 50 ? ? ? ? ?
le79r79 data sheet 20 zarlink semiconductor inc. le79r79 test circuit note: 1. refer to the applications circuit on the next page for recommended configuration. 2. the input should be 50% duty cycle cmos-compatible input. rtrip1 c hp ryout1 ryout2 b at 1 ryout1 ryout2 vbat2 vcc rd vtx +5 v r d r t rdcr le79r79 v tx v rx rsn r rx r dc2 r dc1 rtrip2 r rt1 430 k ? ? - 5 v vneg 75 k ? ? ? ? ? ? ?
le79r79 data sheet 21 zarlink semiconductor inc. application circuit note: the input should be 50% duty cycle cmos-compatible input. rtrip1 c hp ryout1 ryout2 bat1 ryout1 ryout2 vbat2 vcc rd vtx +5 v r d rdcr u1 le79r79 v tx v rx rsn r rx r dc1 r dc2 c dcr rtrip2 r rt1 515 k ? ? - 5 v vneg 66 k ? ? ? ? ? ? ? ? ? ? ? - 70 v v bat1, - 24 v v bat2 high battery loop threshold ringing loop threshold two-wire impedance, 600 ? ? ? ?
le79r79 data sheet 22 zarlink semiconductor inc. physical dimensions 32-pin plcc note: packages may have mold tooling markings on the surface. these ma rkings have no impact on the form, fit or function of the device. markings will vary with the mold tool used in manufacturing. notes: 1 dimensioning and tolerancing conform to asme y14,5m-1994. 2 to be measured at seating plan - c - contact point. 3 dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.010 inch per side. dimensions d and e include mold mismatch and determined at the parting line; that is d1 and e1 are measured at the extreme material condition at the upper or lower parting line. 4 exact shape of this feature is optional. 5 details of pin 1 identifier are optional but must be located within the zone indicated. 6 sum of dam bar protrusions to be 0.007 max per lead. 7 controlling dimension : inch. 8 reference document : jedec ms-016 32-pin plcc jedec # ms-016 s y mbol min nom max a 0.125 -- 0.140 a1 0.075 0.090 0.095 d 0.485 0.490 0.495 d1 0.447 0.450 0.453 d2 e 0.585 0.590 0.595 e1 0.547 0.550 0.553 e2 & 0 deg -- 10 deg 32-pin plcc 0.205 ref 0.255 ref
le79r79 data sheet 23 zarlink semiconductor inc. 32-pin qfn note: packages may have mold tooling markings on the surface. these ma rkings have no impact on the form, fit or function of the device. markings will vary with the mold tool used in manufacturing. notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. is in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jep 95-1 and ssp-012. details of the t erminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. coplanarity applies to the exposed pad as well as the terminals. 6. reference document: jedec mo-220. 7. lead width deviates from the jedec mo-220 standard. 32-pin qfn min nom max a 0.80 0.90 1.00 a2 b 0.18 0.23 0.28 d d2 5.70 5.80 5.90 e e2 5.70 5.80 5.90 e l 0.43 0.53 0.63 n a1 0.00 0.02 0.05 a3 aaa bbb ccc 0.57 ref 32 lead qfn symbol 0.10 0.10 0.20 0.20 ref 32 0.80 bsc 8.00 bsc 8.00 bsc
le79r79 data sheet 24 zarlink semiconductor inc. revision history revision b to c ? minor changes were made to the data sheet st yle and format to conform to zarlink standards. ? electrical characteristics; last row under ring signal, min changed from 130 to 150, typ changed from 160 to 180, and max changed from 190 to 210. ? slic decoding table; added b2en reference to the battery se lection column and its corresponding note to the notes sec- tion. ? applications circuit; revised revision c to d ? minor changes were made to the data sheet st yle and format to conform to zarlink standards. revision d to e ? on pages 17 and 18, r dc1 and r dc2 were switched. revision e to f ? the physical dimensions (pl032) were added to the physical dimensions section. ? deleted the ceramic dip and plastic di p packages and references to them. ? updated the pin description table to correct inconsistencies. revision f to g ? the equation on page 13 was changed: from: to: revision g to h ? in ?ordering information? secti on, added description for wafer fo undry facility optional character. revision h to i ? updated document format ? added opns for qfn package to ordering information table ? added physical dimensions for 8x8 qfn package revision i to j1 ? added green package opn to ordering information , on page 1 ? added package assembly , on page 7 ? updated document format revision j1 to k1 ? added note 3 to connection diagrams , on page 5 revision k1 to l1 ? added "packing" column and note 2 and 4 to ordering information , on page 1 ? updated 32qfn drawing in physical dimensions , on page 22 revision l1 to m1 ? added option for plcc green package to ordering information , on page 1 ? added option for qfn green package for dash grades 2 through 4 in ordering information , on page 1 ? added note to physical dimensions , on page 22 r rt1 300 cf v bat1 vbat 3.5 ?15 p a 300 cf r lrt 150 2r f ++ x x x ? ------------------------------------------------------------------------------------------------------------------------------- ---------- - x x r lrt 150 2r f ++ x = r rt1 320 cf v bat1 vbat 5 ?24 p a 320 cf r lrt 150 2r f ++ x x x ? ------------------------------------------------------------------------------------------------------------------------------- ------ x x r lrt 150 2r f ++ x =
le79r79 data sheet 25 zarlink semiconductor inc. revision m1 to n1 ? removed opns for all non-green packaged parts from ordering information , on page 1 ? removed 79r79-3qc, 79r79-4jc and 79r79-4qc from ordering information , on page 1 revision n1 to n2 ? removed reference to le79r79-4 option from ordering information , on page 1 revision n2 to o1 ? changed i l loop-current accuracy from 0.915 to 0.87 in electrical characteristics . revision o1 to o2 ? enhanced format of package drawings in physical dimensions , on page 22 ? added new headers/footers due to zarlink purchase of legerity on august 3, 2007
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of prod uct or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any pu rpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to pe rform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl, the zarlink semiconductor logo and the legerity logo and combinations thereof, voiceedge, voiceport, slac, islic, islac and voicepath are trademarks of zarlink semiconductor inc. technical documentation - not for resale for more information ab out all zarlink products visit our web site at

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